CPiLD is a CPLD board for Raspberry Pi based on a Xilinx XC9572XL in a 64 pin package.
This chip is 5 volt tolerant. The board also has an I2C buffer to give the I2C bus 5 volt tolerance.
CPLDs can be used for many things. They are made up of logic gates. Interface conversion and buffering are common uses.
The CPiLD default image provides an I/O expansion as well as buffering of the regular Raspberry Pi GPIO signals.
CPiLD allows for easy breadboarding with fewer wires as it can reroute pins. It also provides a simple board to learn about logic circuits and hardware description languages.
The board has a switch and two LEDs in addition to the logic chips. Optional placements on the rear of the board allow for a clock and local LDOs rather than using the 3.3V rail of Raspberry-Pi.
The board is currently beta, please leave a comment on this blog post if you like the board and would chip into a kickstarter to make a batch of them (at a reasonable price of course). Leave a real email so I can contact you when the kickstarter starts.
Over a SPI mode 0 interface the default image provides 16 bit addressable outputs and 8 inputs. (When you send a SPI byte you are returned the inputs). You can find the XSVF image and VHDL file here. The file VHDL code isn't yet final however.
CPiLD is programmed via 4 GPIOs of Raspberry Pi and a port of Xilinx's XSVF player available here.
The schematic for CPiLD Rev 2 can be found here.
The KiCAD project files for Rev 2 will be posted when Rev 2 is tested to be bug free. The board above (Rev 1) was missing a resistor and had an awkward clearance for the rear side clock with the female header mounted.